Process for producing chip

ABSTRACT

A process for producing a chip in which plural ejection orifice arrays are arranged including conducting reduction projection exposure plural times to a wafer having a substrate and a photosensitive resin layer formed thereon while relatively moving positions of the wafer and a reticle to form ejection orifice array patterns in the resin layer, developing the patterns to form ejection orifice arrays in the resin layer, and dividing the wafer to form plural chips in which the plural ejection orifice arrays are arranged. The exposure is conducted once to form in the resin layer a first ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction thereof in one chip, a second ejection orifice array pattern corresponding to all ejection orifice arrays in one chip and a third ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction thereof in one chip.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a process for producing a chip.

2. Description of the Related Art

As an example of a liquid ejection head from which a liquid is ejected,an ink jet recording head used in an ink jet recording system ismentioned. The ink jet recording head has a chip generally provided witha flow path, a heat-generating element provided in a part of the flowpath for generating energy for ejecting an ink, and a minute inkejection orifice for ejecting the ink. A process for producing such achip includes the following steps:

a step of forming a pattern of a flow path with a photosensitivematerial on a substrate on which a heat-generating element has beenformed and then applying and forming a coating resin layer which willbecome a flow path forming member with a photosensitive material on thesubstrate so as to coat the pattern; anda step of forming an ejection orifice in the coating resin layerobtained in the above step and then removing the photosensitive materialused in the pattern to form the flow path.

According to this production process, minute processing as to theformation of the flow path and the ejection orifice becomes feasiblewith extremely high accuracy because a photolithographic method used ina semiconductor field is applied thereto. In this production process,patterning by exposure by means of a semiconductor exposure apparatus isused as a method for forming the photosensitive material into anintended shape upon the formation of the ejection orifice. When anegative photosensitive material is used, a shadow is prepared into ashape intended to be formed by, for example, a reticle, and exposure isconducted through the semiconductor exposure apparatus, whereby thephotosensitive material of a portion where the shadow has been preparedand light has not been applied is not cured and removed in a removalstep.

On the other hand, as a process for improving the productivity of achip, a process in which a great number of liquid ejection heads arefabricated as chips on a wafer such as an Si wafer, and respective chipsare divided by cutting to obtain individual liquid ejection heads isused. According to this process, the plural chips can be treatedsuccessively or at a time under the same conditions in the respectiveproduction steps, and so the efficiency of production can be improved.For example, when an intended structure is fabricated in the respectivechips by exposure and development for the photosensitive material,exposure of the same exposure pattern can be successively conducted forthe respective chips by means of a reticle of an exposure apparatus,whereby the exposure treatment can be conducted with good efficiency.

In recent years, the length of a chip has been made longer for achievinghigh-speed printing. In addition, the number of ejection orifice arrays(also referred to as nozzle arrays) taking charge of different colors isalso increased with the increase in the kinds of inks for expanding acolor gamut in photo-printing, and the breadth of the chip is alsowidened owing to the increase in the nozzle arrays corresponding torespective colors. As a result, an area per chip comes to increase.Under such circumstances, a pattern is arranged for use up to theneighborhood of the margin of a field angle of a reticle for the purposeof exposing plural chips at a time for shortening process time andreducing the number of times of exposure. As a result, when reductionprojection exposure is conducted, light transmitted through a portionhigh in curvature of a lens in a projection lens system within asemiconductor exposure apparatus is influenced by lens aberrations togreatly affect the finish of ejection orifice formation in some cases.It means that when the light from the semiconductor exposure apparatusis adjusted so as to exactly form a pattern utilizing a part around acenter of the reticle, exposure is conducted at a position of outsidedistortion with respect to an ideal lattice with increasing distancefrom the part around the center of the reticle. An example thereof istypically illustrated in FIGS. 1A and 1B. FIG. 1A illustrates ideallattice patterns provided on the whole surface within the field angle ofthe reticle, and a solid-line portion becomes a light shielding portion.FIG. 1B illustrates that a pattern obtained in the case where theexposure is conducted by means of this reticle and formed of an actuallight shielding portion on an object to be exposed has a portiondistorted from the ideal lattice pattern. That is to say, when a patternis formed in the neighborhood of the margin of a field angle of areticle of a stepper exposure apparatus, and a chip is exposed to lighthaving passed through that pattern to form an ejection orifice, therehas been caused such a problem that the position of the ejection orificedeviates outside from the center of the reticle.

Regarding such an optical problem, Japanese Patent Application Laid-OpenNo. 2001-264637 (Patent Literature 1) discloses means for basicallycorrecting the above-described aberrations by devising a lens system.According to this means, a spherical aberration-correcting opticalsystem is installed in the inside and detachably mounted on the side ofan image of an objective lens, and a lens group closest to the side ofan object has negative refracting power and is moved in a direction ofan optical axis, whereby the spherical aberration can be corrected.

SUMMARY OF THE INVENTION

According to the present invention, there is provided a process forproducing a chip in which plural ejection orifice arrays are arranged,the process comprising the steps of conducting reduction projectionexposure plural times to a wafer having a substrate and a photosensitiveresin layer formed on the substrate while relatively moving positions ofthe wafer and a reticle to form ejection orifice array patterns in thephotosensitive resin layer, developing the ejection orifice arraypatterns to form ejection orifice arrays in the photosensitive resinlayer, and dividing the wafer having the photosensitive resin layer inwhich the ejection orifice arrays have been formed to form plural chipsin which the plural ejection orifice arrays are arranged, wherein thereduction projection exposure is conducted once to in the photosensitiveresin layer form a first ejection orifice array pattern corresponding topartial ejection orifice arrays in an arranging direction of ejectionorifice arrays in one chip, a second ejection orifice array patterncorresponding to all ejection orifice arrays in another one chip and athird ejection orifice array pattern corresponding to partial ejectionorifices array in an arranging direction of ejection orifice arrays in afurther one chip.

Further features of the present invention will become apparent from thefollowing description of exemplary embodiments with reference to theattached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates ideal lattice patterns provided on the whole surfacewithin a field angle of a reticle in a semiconductor exposure apparatus,and FIG. 1B is an imaginary view illustrating the image that an ideallattice position is distorted outside with increasing distance from thecenter of the reticle in the semiconductor exposure apparatus.

FIG. 2 is an explanatory view of a conventional embodiment andillustrates the state that exposure is conducted to chips on a siliconwafer by means of a reticle.

FIGS. 3A, 3B and 3C are explanatory views of another conventionalembodiment and illustrate a reticle for exposing two chips adjoiningeach other of a chip array on a silicon wafer and the chips exposed bythe reticle.

FIGS. 4A, 4B and 4C are explanatory views of a further conventionalembodiment and illustrate a reticle for exposing four chips adjoiningeach other of two chip arrays arranged in parallel on a silicon waferand the chips exposed by the reticle.

FIGS. 5A, 5B and 5C are explanatory views of a still furtherconventional embodiment and illustrate formation of dots upon printingusing a chip exposed by a conventional reticle, in which FIG. 5Aillustrates an arrangement state of ejection orifice arrays formed inthe chip, FIG. 5B illustrates the state of dot filling per pixel, andFIG. 5C illustrates the state of dot filling per pixel after driving iscorrected in a head-scanning direction.

FIG. 6 is an explanatory view of an embodiment of the present inventionand illustrates the state that exposure is conducted to chips on asilicon wafer by means of a reticle.

FIGS. 7A, 7B and 7C are explanatory views of a first embodiment of thepresent invention and illustrate a reticle for exposing two chipsadjoining each other of a chip array on a silicon wafer and the chipsexposed by the reticle.

FIGS. 8A, 8B and 8C are explanatory views of the first embodiment of thepresent invention and illustrate a reticle for exposing four chipsadjoining each other of two chip arrays arranged in parallel on asilicon wafer and the chips exposed by the reticle.

FIG. 9 is an explanatory view of a yet still further conventionalembodiment and illustrates the external form of a typical chip and thestructure thereof.

FIG. 10 is an explanatory view of a yet still further conventionalembodiment and illustrates the external form of a typical head and thestructure thereof.

FIGS. 11A, 11B and 11C are explanatory views of a second embodiment ofthe present invention and illustrate a reticle for exposing chips on asilicon wafer and the chips exposed by the reticle.

FIGS. 12A, 12B and 12C are explanatory views of a third embodiment ofthe present invention and illustrate a reticle for exposing chips on asilicon wafer and the chips exposed by the reticle.

FIGS. 13A, 13B and 13C are explanatory views of the first embodiment andillustrate formation of dots upon printing using a chip exposed througha pattern located at the center of the reticle according to the firstembodiment, in which FIG. 13A illustrates an arranged state of ejectionorifice arrays formed in the chip, FIG. 13B illustrates the state of dotfilling per pixel, and FIG. 13C illustrates the state of dot filling perpixel after driving is corrected in a head-scanning direction.

FIGS. 14A, 14B and 14C are explanatory views of the first embodiment andillustrate formation of dots upon printing using a chip exposed twicethrough patterns located at a left half and a right half of the reticleaccording to the first embodiment, in which FIG. 14A illustrates anarranged state of ejection orifice arrays formed in the chip, FIG. 14Billustrates the state of dot filling per pixel, and FIG. 14C illustratesthe state of dot filling per pixel after driving is corrected in ahead-scanning direction.

DESCRIPTION OF THE EMBODIMENTS

Preferred embodiments of the present invention will now be described indetail in accordance with the accompanying drawings.

The present inventors have obtained new knowledge that the fundamentaloptical phenomenon described above with reference to FIGS. 1A and 1Baffects a chip and generates the cause of color unevenness upon printingin the case where the liquid ejection head is used for ink jetrecording. Specifically, in order to form a chip provided with ejectionorifice arrays extending in a long side direction, two chips arranged upand down or left and right with a center of a field angle of a reticleof an exposure apparatus regarded as a center line extending to the samedirection as the ejection orifice array are arranged in line symmetry toconduct reduction projection exposure. Thus, between an ejection orificearray close to the center of the reticle and an ejection orifice arraydistant from the center, a great difference in the distance from thefirst ejection orifice to the last ejection orifice of the ejectionorifice array (hereinafter also referred to as a total pitch) may becaused in some cases under the influence of the above-described opticalphenomenon. When an ink jet recording head having a chip which makessuch a difference in the total pitch is used to conduct color recording,dot shift occurs in a pixel to be formed, and consequently colorunevenness occurs.

On the other hand, the correction can be conducted by the lens system ofthe exposure apparatus as described in Patent Literature 1. It ishowever difficult to form a chip in a short period of time with goodaccuracy when a process time for matching conditions of the lens systemfor every product, investment in a new lens system and maintainabilityare considered.

It is an object of the present invention to solve the above-describedproblems. That is to say, the object of the present invention is toprovide a process for producing a chip, by which a batch exposure toplural chips is possible even when distortion from an ideal exposurepattern occurs on an exposure pattern to an object to be exposed, andthe field angle of a reticle can be used to the utmost to improveproduction efficiency.

The present invention relates to a process for producing a chip in whichplural ejection orifice arrays are arranged. In the production processaccording to the present invention, at least one liquid ejection head isfabricated as a rectangular chip in, for example, a chip section of awafer for cutting out of a chip assigned for one liquid ejection head.After completion of the formation of an intended structure in respectivechips, the respective chips are cut out of the wafer and divided intoindividual chips. That is to say, the wafer is divided, whereby pluralchips in which plural ejection orifice arrays are arranged are formed.The liquid ejection head fabricated in each chip has a structure whereplural ejection orifice arrays extending in a long side direction of therectangular chip are arranged in parallel. In addition, the respectivechips on the wafer are arranged in a direction parallel to this ejectionorifice array (lateral direction), whereby a chip array is formed.Incidentally, plural chip arrays may be arranged repeatedly in a longside direction (vertical direction) of the respective chips, i.e. anextending direction of the ejection orifice array.

An exposure treatment is successively conducted at a predeterminedposition while relatively moving a reticle of an exposure apparatuswhich has a field angle corresponding to a region to be subjected to anexposure treatment of the rectangular chip with respect to the waferalong the chip array. The wafer has a substrate formed of, for example,silicon and a photosensitive resin layer formed on the substrate, andthe photosensitive resin layer is exposed. The reduction projectionexposure is conducted plural times while relatively moving positions ofthe wafer and the reticle. The relative movement of the reticle to thewafer can be conducted by moving at least one of the reticle and thewafer.

With respect to the relation between the moving direction of the reticleand the exposure treatment, when a direction from the left of the chiparray to the right is regarded as a first path and the reverse directionis regarded as a second path whether the exposure to each chip isconducted in the first path, or the exposure to each chip is conductedin the second path is not limited. Whether the exposure is conducted inthe first path or in the second path can be selected according toconditions for an exposure operation. The same applies to an exposureoperation when each chip array is subjected to the exposure treatment orplural chip arrays are subjected to the exposure treatment at a time inthe case where the plural chip arrays are present.

The exposure conducted in the present invention is reduction projectionexposure. As the exposure apparatus used in the present invention, astepper-type exposure apparatus using a reticle in which patterns forexposure are provided in a field angle is suitably used. After ejectionorifice array patterns are formed in a photosensitive resin layer, theejection orifice array patterns are developed, thereby forming ejectionorifice arrays in the photosensitive resin layer. Thereafter, the waferis divided to form plural chips in which plural ejection orifice arraysare arranged.

The reticle used in the present invention has, in a field angle thereof,an exposure pattern in which two overall chip patterns are arranged asexposure patterns necessary for forming plural ejection orifice arraysarranged in parallel in one chip. More specifically, the reticle has afirst ejection orifice array pattern corresponding to partial ejectionorifice arrays in an arranging direction of ejection orifice arrays inone chip, a second ejection orifice array pattern corresponding to allejection orifice arrays in another one chip and a third ejection orificearray pattern corresponding to partial ejection orifice arrays in anarranging direction of ejection orifice arrays in a further one chip.

The second ejection orifice array pattern (overall chip pattern) is usedfor conducting exposure to the whole of one chip section in which atleast one chip is arranged on a wafer. This chip section may beconstituted by one chip as illustrated in FIG. 3A and FIG. 7A or byselecting, as one section, plural chips arranged in series in a verticaldirection (long side direction to which an ejection orifice arrayextends) of plural chip arrays arranged in parallel as illustrated inFIG. 4A and FIG. 8A. The number of chips in the case where one chipsection is constituted by plural chips may be suitably selectedaccording to the size of the reticle field angle. In embodimentsillustrated in FIG. 4A and FIG. 8A, the chip section is constituted bytwo chips arranged in series in the vertical direction.

The center of the overall chip pattern used for forming the ejectionorifice arrays in one chip is positioned so as to be arranged at asubstantial center of the reticle. Additionally, a first side and asecond side are present on both sides of the overall chip pattern, and asubstantially half chip pattern (first ejection orifice array pattern)on the second side and a substantially half chip pattern (third ejectionorifice array pattern) on the first side are respectively laid out onthe first side of the overall chip pattern and on the second side of theoverall chip pattern, thereby laying out these halves on both sides ofthe overall chip pattern.

Specifically, two overall chip patterns are provided, and one overallchip pattern thereof is divided into a first half portion and a secondhalf portion in the moving direction of the reticle to obtain a firsthalf chip pattern and a second half chip pattern. The overall chippattern is then regarded as a center portion in the moving direction ofthe reticle, and the first half chip pattern and the second half chippattern are arranged at the first half portion and at the second halfportion across the center portion, respectively, to thereby obtain anexposure pattern in the reticle. The exposure is conducted once to formin the photosensitive resin layer a first ejection orifice array patterncorresponding to partial ejection orifice arrays in an arrangingdirection of ejection orifice arrays in one chip, a second ejectionorifice array pattern corresponding to all ejection orifice arrays inanother one chip and a third ejection orifice array patterncorresponding to partial ejection orifice arrays in an arrangingdirection of ejection orifice arrays in a further one chip. An ejectionorifice array pattern corresponding to all ejection orifice array in onechip is formed by the first ejection orifice array pattern formed by theone exposure and a third ejection orifice array pattern formed by nextone exposure conducted after positions of the wafer and the reticle arerelatively moved.

A dividing position (dividing line) between the first half chip patternand the second half chip pattern in the overall chip pattern may be setso as to satisfy the following requirements (A) and (B) and has no needto be an exact center portion of the overall chip pattern in the movingdirection of the reticle. The first ejection orifice array pattern andthe third ejection orifice array pattern favorably have an ejectionorifice array pattern corresponding to half of all ejection orificearrays in one chip.

(A) The total pitch difference between plural ejection orifice arrayswithin one chip in a completed flow path forming member can becontrolled within an effective range for preventing occurrence of colorunevenness.(B) Plural ejection orifice arrays in one chip include ejection orificearrays arranged in line symmetry to a center line in a paralleldirection of the ejection orifice arrays.

Incidentally, as examples of the linearly symmetrical arrangement of theejection orifice arrays of the above condition (B), the followingarrangements may be mentioned.

Arrangement 1:

Arrangement in which one ejection orifice array is arranged on thecenter line, and other plural ejection orifice arrays are arranged inline symmetry to this center line.

Arrangement 2:

Arrangement in which the center line is positioned at a portion where noejection orifice array is arranged, and plural ejection orifice arraysare arranged in line symmetry to this center line.

The second ejection orifice array pattern has an ejection orifice arraypattern corresponding to three or more ejection orifice arrays, and thethree or more ejection orifice arrays include ejection orifice arraysfor respectively ejecting liquids of different colors, and the ejectionorifice arrays are favorably arranged in such a manner that the colorarrangement of the liquids becomes line symmetry when viewed from anejection orifice array located at the center. In addition, an ejectionorifice array (C) for ejecting a cyan ink, an ejection orifice array (M)for ejecting a magenta ink and an ejection orifice array (Y) forejecting a yellow ink are each favorably constituted by two ejectionorifice arrays.

Such a constitution that one or more ejection orifice arrays which donot become line symmetry are added in addition to the ejection orificearrays located at linearly symmetrical positions may also be employed.As an example of Arrangement 1, such ejection orifice arrays that whenan ink jet recording head having ejection orifice arrays for threecolors of, for example, yellow (Y), magenta (M) and cyan (C) isreciprocatingly moved in a direction intersecting the ejection orificearrays to conduct bi-directional printing, the arrangement of theejection orifice arrays is CMYMC may be mentioned.

Incidentally, the ejection orifice array taking charge of each color maybe of a double array formed of two ejection orifice arrays close to eachother in each color as illustrated in FIG. 3A, FIG. 4A, FIG. 7A, FIG.8A, FIG. 9, FIG. 11A and FIG. 12A. As illustrated in FIG. 12A and FIG.14A, the center line of line symmetry may be put on a position dividingthis double array as illustrated in FIG. 12A and FIG. 14A to lay out thefirst half chip pattern and the second half chip pattern on the reticle.

The reticle having the exposure pattern of the above-describedconstitution according to the present invention is used to expose thechip array, whereby the total pitch difference between plural ejectionorifice arrays provided within one chip can be effectively reduced. As aresult, influence by the structure of a liquid ejection head on theoccurrence of color unevenness upon color printing using inks can bereduced.

In addition, even when distortion occurs on an exposure pattern in apart to be exposed distant from the center portion of the reticle, thedistance ratio between respective ejection orifice arrays in a lateraldirection at an arbitrary position of the respective ejection orificearrays arranged in line symmetry and in parallel is almost constantaccording to the distortion. As a result, control for preventing colorunevenness in formation of ink dots in a pixel upon printing becomeseasy as illustrated in FIGS. 13B and 13C, and FIGS. 14B and 14C.

Arrangement of the reticle of the above-described constitution on awafer is conducted by aligning a center of the field angle of thereticle with a center of a chip section for a chip to be subjected tothe exposure treatment. By this alignment, the overall chip pattern isarranged on one chip section, and the first half chip pattern and thesecond half chip pattern are arranged on a left half of a chip sectionneighbor to the right of that chip section and a right half of a chipsection neighbor to the left, respectively. Accordingly, one reticlefield angle is arranged over neighboring three chip sections. By theexposure treatment under this state, the second half of the chip sectionneighbor to the right of the chip section with which the center of thereticle field angle has been aligned, that is, of the chip sectionlocated ahead of the moving direction of the reticle, is exposed, andthe first half of the chip section neighbor to the left, that is, of thechip section located backward of the moving direction of the reticle, isexposed. The chip section with which the center of the reticle fieldangle has been aligned, and parts of the respective chip sectionsneighbor to that chip section are exposed at a time in this manner.

Since the left half of the chip section neighbor to the right of thechip section with which the center of the reticle field angle has beenaligned has been already subjected to the exposure treatment by theabove exposure treatment, the center of the reticle is aligned withrespect to a chip section neighbor to the right of this chip sectionwith this chip section skipped upon the next exposure treatment.

One reticle field angle is arranged on non-exposed portions ofneighboring three chip sections by doing so, and the second half chippattern can be arranged on a non-exposed right half of the chip sectionin which the left half has been already subjected to the exposuretreatment. By the exposure treatment under this state, the exposure ofthe remaining right half of the chip section in which the left half hasbeen already subjected to the exposure treatment can be completed.

As described above, the alignment of the center of the reticle isconducted for every other chip of the chip array, and the exposuretreatment is successively conducted repeatedly, whereby the whole chiparray can be subjected to the exposure treatment.

In the above description, the description regarding the going directionof the reticle has been made. However, the exposure treatment can becompleted by the same operation even when the exposure treatment isconducted by the returning movement.

As the liquid ejection head, there may be mentioned a head having such astructure that a flow path forming member in which plural ejectionorifice arrays and a flow path for supplying a liquid to respectiveejection orifices constituting an ejection orifice array are formed isarranged on a substrate provided with ejection-energy-generatingelements corresponding to the respective ejection orifices. Aheat-generating element utilizing heat as ejection energy or a piezoelement utilizing vibration may be used as theejection-energy-generating element.

The steps up to the formation of the ejection orifice arrays in eachchip may be selected according to a structure of the intended liquidejection head and a production process suitable for the structurethereof. As examples of a process for forming the flow path formingmember on the substrate, there may be mentioned various publicly knownprocesses, for example, the following processes. For example, theabove-described exposure treatment by the reticle may be applied to acoating resin layer for forming a flow path forming member obtained byconducting respective steps in the following respective processes toeach chip on a wafer at a time.

(A) A Process Using a Solid Layer which Will Become a Form of the FlowPath Forming Member.As an example of the process using the solid layer which will become aform of the flow path forming member, Process (I) having the followingsteps (1) to (6) may be mentioned. Process (I):(1) A step of providing an ejection-energy-generating element on asubstrate.(2) A step of covering the ejection-energy-generating element on thesubstrate to form a solid layer as a form occupying a portion which willbecome a flow path.(3) A step of forming a coating resin layer formed of a photosensitivematerial for forming the flow path forming member covering the solidlayer.(4) A step of subjecting the coating resin layer to an exposuretreatment and a development treatment to form an ejection orifice array.(5) A step of providing a piercing aperture which will become a supplyport for supplying a liquid to the flow path from a back side of thesubstrate.(6) A step of removing the solid layer on the substrate using thepiercing aperture to form the flow path.Incidentally, the order of the steps (4) to (6) may be changed.

The photosensitive material for forming the coating resin layer(photosensitive resin layer) may be selected according to the structureof a liquid ejection head, which is an object of production, and aproduction process thereof. As an example, a positive photosensitiveresin such as poly(methyl isopropenyl ketone) is used as a material forforming the solid layer, and exposure and development are conductedaccording to information, whereby a solid layer of a desired form can bearranged on the substrate. In addition, a negative photosensitive resincomposition may be used as a material for forming the coating resinlayer. The coating resin layer becomes an ejection orifice formingmember and is formed by, for example, an epoxy resin, a photo-inducedcationic polymerization initiator, a sensitizer and methyl isobutylketone.

(B) A Process of Forming an Orifice Plate Utilizing a Filling Layer(Sacrifice Layer) after Formation of a Flow Path Wall.

As an example of the process of forming the orifice plate utilizing thefilling layer (sacrifice layer) after formation of the flow path wall,Process (II) having the following steps (1) to (7) may be mentioned.Process (II):

(1) A step of providing an ejection-energy-generating element on asubstrate.(2) A step of providing a flow path wall on the substrate on which theejection-energy-generating element has been provided.(3) A step of filling a filling material (sacrifice layer) in a portionwhich is surrounded by the flow path wall and will become a flow path.(4) A step of forming a layer for an orifice plate with a photosensitivematerial on a surface formed by the flow path wall and the fillingmaterial (sacrifice layer).(5) A step of subjecting the layer for the orifice plate to an exposuretreatment and a development treatment to form an ejection orifice array.(6) A step of providing a piercing aperture which will become a supplyport for supplying a liquid to the flow path from a back side of thesubstrate.(7) A step of removing the filling material (sacrifice layer) on thesubstrate using the piercing aperture to form the flow path.In the above-described process, the flow path forming member isconstituted by the flow path wall and the orifice plate (ejectionorifice plate).

These processes are disclosed in, for example, Japanese PatentApplication Laid-Open No. 2005-205916. According to the processdescribed in this publication, after the flow path wall is covered withthe filling material (sacrifice layer) to conduct a filling step, anupper surface thereof is then flattened to expose an upper surface ofthe flaw path wall, and the orifice plate (plate for forming an ejectionorifice) is then formed. As described above, various steps may be addedas needed.

The photosensitive material for forming the coating resin layer may beselected according to the structure of a liquid ejection head, which isan object of production, and a production process thereof.

The liquid ejection head may be any head so far as the head has such astructure that a chip array capable of being divided from the wafer canbe formed, and exposure and development treatments for forming anejection orifice array can be conducted to each chip on the wafer, andthe production process according to the present invention can be appliedto liquid ejection heads of various structures.

Embodiments of the present invention will hereinafter be described withreference to the drawings.

A liquid ejection head of an ink jet recording apparatus to which thisembodiment can be applied is first described with reference to FIGS. 9and 10.

The liquid ejection head produced by this embodiment is, for example,such a head as illustrated in FIG. 10. FIG. 10 illustrates a head 13 inwhich two different chips 31 and 32 are installed. This embodiment isnot limited to the constitution illustrated in this drawing and mayinclude a head in which a single chip or three or more chips areinstalled. FIG. 9 illustrates the constitution of a typical chip of thechips installed in the head illustrated in FIG. 10. Heat-generatingelements utilized for ejecting an ink are arranged at predeterminedintervals in this chip 3, and a supply port 12 that passes through asubstrate from a back side of the substrate for supplying an ink isopened between two arrays of the heat-generating elements 11. Inaddition, ejection orifices 4 opening above the respectiveheat-generating elements 11 and individual ink flow paths communicatingwith the respective ejection orifices 4 from the supply port 12 areformed on the chip 13 by a cured film of a photosensitive resin. Thisliquid ejection head is arranged in such a manner that a surface onwhich the ejection orifices are formed faces a recording surface of arecording medium. In this liquid ejection head, a pressure generated bythe heat-generating element is applied to an ink filled in the flow paththrough the ink supply port to eject an ink droplet from the ejectionorifice, and this ink droplet is applied to a recording medium, therebyconducting recording. Incidentally, FIG. 9 illustrates the case wherethere are three ejection orifice arrays. However, the present inventionis not limited to the constitution of this drawing so far as the numberof arrays is plural (2 or more).

An example of a process for producing the liquid ejection head willhereinafter be described.

After a flow path (not illustrated) and the like are formed in eachsection which will become a chip 3 of a silicon wafer as a wafer 1 forcutting out of a chip in which a heat-generating element (notillustrated) has been arranged, a negative photosensitive resin film 2is formed as illustrated in FIG. 2, and an exposure treatment issuccessively conducted to a portion of the photosensitive resin film 2located on the heat-generating element by moving a reticle 5 having anexposure pattern for forming an ejection orifice array in a direction ofthe arrow X. After the exposure treatment to respective chips iscompleted, a development treatment is conducted at a time on the waferto obtain a flow path forming member which is formed of a cured film ofthe photosensitive resin and in which an ejection orifice array isarranged at a predetermined position in the respective chips 3.

A method such as a spin coating method, a roll coating method or a slitcoating method may be used for forming the photosensitive resin film.Incidentally, the above-described mode of providing the pattern whichwill become the form of the flow path may also be used. Both the methodof providing the pattern which will become the form and the methodmaking no use of the form are included in the present invention.

In addition, an ink repellent layer having negative photosensitivity maybe formed on the photosensitive resin layer as needed. The ink repellentlayer can be formed by a coating method such as a spin coating method, aroll coating method or a slit coating method. However, since the inkrepellent layer is formed on an uncured negative photosensitive resinfilm in this embodiment, both layers are favorably not compatible witheach other more than necessary.

A light condensation type exposure apparatus may be suitably used forthe exposure treatment by the reticle, and the reduction rate of thelight condensation type exposure apparatus may be controlled to, forexample, about ½ to 1/10.

The present inventors have found that a new problem of occurrence ofcolor unevenness upon printing using an ink jet recording head obtainedby using the exposure apparatus using such an optical system is caused.This problem is described taking a case where chips each having threeejection orifice arrays constitute a chip array as an example. FIGS. 3A,3B and 3C illustrate a case where neighboring two chip sectionscorresponding to two chips are provided within a field angle 5 a of areticle 5 for arranging first to third ejection orifice arrays 4 a, 4 band 4 c in parallel in each of chips 3 a and 3 b neighboring left andright, and an ejection orifice array pattern 6 a for conducting a batchexposure to these chip sections is used. FIG. 3A includes an enlargedview (FIG. 3C) of an ejection orifice pattern. Incidentally, an enlargedview of an ejection orifice pattern is likewise added to with respect toFIGS. 4A, 7A, 8A, 11A and 12A. When exposure is conducted by using thisreticle 5, a difference is caused between an ejection orifice arrayclose to the center of the reticle 5 and an ejection orifice arraydistant from the center in a total pitch from the first ejection orificeto the last ejection orifice of the ejection orifice array in the twochips 3 a, 3 b after the exposure as illustrated in FIG. 3B. Even in adirection perpendicular to the ejection orifice array, dislocation D inan outward direction to the center 5 b of the reticle occurs on anejection orifice closer to the end of the ejection orifice array.

FIGS. 4A, 4B and 4C illustrate a case where one chip section is set fortwo chips arranged in series in a vertical direction in two chip arrays.In FIG. 4B, one chip section is constituted corresponding to acombination of a chip 3 c and a chip 3 d, another chip section isconstituted corresponding to a combination of a chip 3 e and a chip 3 f.The reticle 5 has an ejection orifice array pattern 6 b for four chipsto be laid out on the two chip sections within one reticle field angle 5a. Even upon an exposure operation using the reticle 5 illustrated inFIG. 4A, the above-described technical problem occurs in the four chips3 c to 3 f after the exposure like the case illustrated in FIG. 3B.

A chip 3 a illustrated in FIG. 5A is a chip which is exposed through aleft reticle pattern illustrated in FIG. 3A and has first to thirdejection orifice arrays 4 a to 4 c. Incidentally, FIG. 3B is a plan viewin which the ejection orifice arrays are illustrated upward in avertical direction in the drawing. On the other hand, FIG. 5Aillustrates a state actually installed in a head. That is to say, FIG.5A is a bottom plan view in which the ejection orifice arrays areillustrated downward in a vertical direction in the drawing (therefore,a drawing turned by 180° along a direction of the ejection orificearray). When such a chip is driven by what is called serial printing(such a printing method that a head is scanned in a directionperpendicular to the ejection orifice array) without controllinganything, dislocation of the ejection orifice array is reflected on theprinting as it is, so that a problem such as dot shift with respect toan original pixel occurs as illustrated in FIG. 5B illustrating thestate of dot filling per pixel. For example, image unevenness by thefollowing phenomenon occurs between the first and last ejection orificesides 4 d and 4 f of the respective ejection orifice arrays, and thecentral ejection orifice side 4 e of the respective ejection orificearrays upon formation of dots by the first to third ejection orificearrays 4 a, 4 b and 4 c.

With respect to the ejection orifices of ejection orifice array ends 4 dand 4 f, dots 8 a, 8 b and 8 c printed by the first to third ejectionorifice arrays shift in both ejection orifice array direction andhorizontal direction (head-scanning direction) with respect topredetermined pixels 7 a and 7 c (the dots shift diagonally to the upperright in the first-side ejection orifices of the ejection orifice arraysand to the lower left in the last-side ejection orifices of the ejectionorifice arrays.)

The pixels 7 a and 7 c in which the dot shift has occurred are differentin dot filling within a pixel from the pixel 7 b corresponding to theejection orifices located at the center 4 e of the ejection orificearrays in which no dot shift occurs.

Incidentally, with respect to the shift in the direction perpendicularto the ejection orifice array direction (head-scanning direction), thedots can be arranged at positions close to the predetermined pixel bycorrecting drive timing as illustrated in FIG. 5C. Alternatively, theshift can be made inconspicuous by dispersing the drive timing atrandom. However, since the dot shift in the ejection orifice arraydirection due to the total pitch difference inevitably occurs in thepredetermined pixel, the image unevenness has been unable to becompletely eliminated.

First Embodiment

The first embodiment of the present invention is illustrated in FIGS.7A, 7B and 7C. The steps before the exposure treatment for forming theejection orifice arrays in each chip are the same as the case describedabove with reference to FIG. 2 and FIGS. 3A, 3B and 3C. That is to say,in this embodiment, the center of an overall chip pattern 6 c used forforming one chip having three arrays of first to third ejection orificearrays is positioned so as to locate at a substantial center withrespect to the center 5 b of a reticle as illustrated in FIG. 7A.Incidentally, a first side and a second side are present on both sidesof the overall chip pattern 6 c, and a substantially half chip patternon the second side and a substantially half chip pattern on the firstside are respectively laid out on the first side of the overall chippattern 6 c and on the second side thereof, thereby laying out thesehalves on both sides of the overall chip pattern 6 c. In FIG. 7A, adirection from the left thereof to the right is a moving direction ofthe reticle along a chip array, a forward half chip pattern in thismoving direction is a first half chip pattern, and a backward half chippattern is a second half chip pattern.

When exposure is conducted by using such a reticle 5 in such a mannerthat a chip pattern laid out at a center fits the external form of achip on a silicon wafer 1 as illustrated in FIG. 6, the chip is exposedthrough the chip pattern of the reticle 5, and at the same timesubstantial halves of two chips on both sides thereof are exposed. Fromthe next exposure, the alignment of the center of the reticle isconducted for every other chip of the chip array so as not to overlapwith a portion exposed once to successively conduct the exposure. As aresult, the remaining halves of the both sides are exposed eventually.FIG. 6 illustrates the state where portions sectioned by exposure jointportions 9 are successively exposed while shifting the reticle by adistance corresponding to two chips in a horizontal direction indicatedby the arrow X in FIG. 6. With respect to the chips which are exposedhalf by half, an overlapping region is favorably provided between aportion first exposed and a portion second exposed taking an exposurealignment error into consideration though not illustrated in FIG. 6. Theoverlapping region does favorably not overlap with an ejection orifice.

As described in FIG. 7B, a chip 3 a of the first kind and a chip 3 b ofthe second kind can be produced by adopting such a production process.In each chip, the difference in the total pitch P1 or P2 between therespective ejection orifice arrays becomes small compared with the totalpitch difference of a conventional chip, so that the image unevennesscan be greatly relieved. The details thereof are as follows.

The chip 3 a illustrated in FIG. 13A is a chip exposed through thereticle pattern located at the center of the reticle illustrated in FIG.7A. The chip 3 b illustrated in FIG. 14A is a chip completed byconducting exposure twice in total through the reticle pattern locatedon the right side or the left side illustrated in FIG. 7A. FIG. 7B is aview in which the ejection orifice arrays are illustrated upward in avertical direction in the drawing. On the other hand, FIG. 13A and FIG.14A illustrate a state of being actually installed in a head, that is,views in which the ejection orifice arrays are illustrated downward in avertical direction in the drawings. When such a chip as illustrated inFIG. 13A or FIG. 14A is driven by what is called serial printing (such aprinting method that a head is scanned in a direction perpendicular tothe ejection orifice array) without controlling anything, dislocation ofthe ejection orifice array is reflected on the printing as it is.According to this embodiment, however, the difference in the total pitchP1 or P2 between the respective ejection orifice arrays is small asdescribed above, so that such great dot shift in the ejection orificearray direction as illustrated in FIG. 5B vanishes. In addition, colorunevenness can be made inconspicuous by, for example, correction ofdrive timing as illustrated in FIG. 13C and FIG. 14C.

Incidentally, when the number of ejection orifice arrays is odd in thechip 3 b of the second kind illustrated in FIG. 14A, the dot shift in adirection perpendicular to the ejection orifice array of the positionsof the respective ejection orifices in the ejection orifice array 4 elocated at the center (scanning direction) may become great in somecases compared with a conventional process. With respect to the shift inthe head-scanning direction, droplets can be arranged at positions closeto the predetermined pixel by correcting drive timing as describedabove. Alternatively, color unevenness can be made inconspicuous bydispersing the drive timing at random as illustrated in FIG. 14C. In theexposure by the reticle laid out in this manner, the regioncorresponding to substantially two chips come to be exposed, so that itgoes without saying that the time of the exposure step does not becomelong compared with a conventional process.

On the other hand, in a case where a chip section is constituted by twochips arranged in series in a vertical direction as illustrated in FIG.8B and two chip sections are exposed by one reticle, that is, four chipsneighboring up and down and left and right are divided, the same effectas that in the case described with reference to FIGS. 7A, 7B and 7C canbe obtained. In other words, the difference in the total pitch P isgreat in the conventional layout of the reticle illustrated in FIG. 4A.However, the difference in the total pitch P1 or P2 becomes small byadopting the constitution illustrated in FIG. 8A, and image unevennesscan be effectively reduced.

Second Embodiment

The second embodiment relating to a bi-directional printing compatiblechip usable in color printing is illustrated in FIGS. 11A, 11B and 11C.In this embodiment, features different from the first embodiment aredescribed. In the second embodiment, a chip has five ejection orificearrays. Ejection orifice arrays for cyan (C), magenta (M) and yellow (Y)that are principal colors were arranged in line symmetry to yellow (Y)as an axis in the order of C, M, Y, M and C in an arranging direction ofa chip array so as not to cause color order unevenness whenbi-directional printing is conducted. When two arrays for cyan or twoarrays for magenta are viewed as a single color as a result of the caseof such a constitution, a difference in the total pitch in therespective arrays is almost 0. With respect to the shift in thehead-scanning direction, these arrays are arranged in line symmetry to areticle center 5 b, so that there is also a merit that image processingof a single color is easy to be conducted. Even in this embodiment, sucha mode that four chips neighboring up and down and left and right aredivided as described in the first embodiment is applied, whereby thesame effect as the first embodiment can be achieved.

Third Embodiment

The third embodiment relating to a bi-directional printing compatiblechip usable in color printing is illustrated in FIGS. 12A, 12B and 12C.In this embodiment, features different from the first embodiment aredescribed. In the third embodiment, a chip has six or more ejectionorifice arrays. Ejection orifice arrays for cyan (C), magenta (M) andyellow (Y) that are principal colors were arranged in line symmetry toyellow (Y) as an axis in the order of C, M, Y, M and C in an arrangingdirection of a chip array so as not to cause color order unevenness whenbi-directional printing is conducted. In this embodiment, for black (Pk)which is not a principal color (relatively small in shot-in ink qualityupon photo-printing and hard to affect the color order unevenness), itis not bi-directional printing compatible.

It is necessary for measures against color unevenness to give priorityto the principal colors great in shot-in ink quality and easy to affectthe color unevenness. That is, it is necessary to decrease the totalpitch difference of the principal colors with priority. Accordingly, theejection orifice arrays are favorably arranged in such a manner that thereticle center 5 b coincides with a substantial center of the Y array todecrease the total pitch difference of the arrays for cyan, magenta andyellow which are principal colors. In addition, when two arrays for cyanor two arrays for magenta are viewed as a single color as a result ofdoing so, a difference in the total pitch in the respective arrays isalmost 0. With respect to the shift in the head-scanning direction,these arrays are arranged in line symmetry to the reticle center, sothat there is also a merit that image processing of a single color iseasy to be conducted.

Gray (Gy) has also come to become a principal color in addition to cyan(C), magenta (M) and yellow (Y) upon formation of a higher-quality photoimage in recent years. That is to say, this embodiment also includesbi-directional printing compatible chips in which Gy is also arranged inline symmetry to yellow as an axis in the order of C, M, Gy, Y, Gy, Mand C. Even in this embodiment, such a mode that four chips neighboringup and down and left and right are divided as described in the firstembodiment is applied, whereby the same effect as the first embodimentcan be achieved.

The chips formed according to the present invention are as follows asillustrated in FIG. 7B and FIG. 8B. One is a chip in which pluralejection orifice arrays are arranged, wherein the length of a centralejection orifice array among ejection orifice arrays constituting theplural ejection orifice arrays is longest, and the ejection orificearrays are arranged in descending order of the length of the ejectionorifice array from the central ejection orifice array toward ejectionorifice arrays on both sides. Another one is a chip in which pluralejection orifice arrays are arranged, wherein the length of a centralejection orifice array among ejection orifice arrays constituting theplural ejection orifice arrays is shortest, and the ejection orificearrays are arranged in ascending order of the length of the ejectionorifice array from the central ejection orifice array toward ejectionorifice arrays on both sides.

These plural ejection orifice arrays include ejection orifice arrays forrespectively ejecting liquids of different colors, and the ejectionorifice arrays are favorably arranged in such a manner that the colorarrangement of the liquids becomes line symmetry when viewed from acentral ejection orifice array.

According to the above-described constitution of the present invention,a batch exposure is conducted to plural chips by devising an exposurepattern provided within a reticle field angle and its position to anobject to be exposed, whereby the time of the exposure step can beshortened, and the exposure treatment can be conducted with goodefficiency. In addition, the total pitch difference between pluralejection orifice arrays provided in one chip can be controlled within atolerable range necessary for effectively preventing occurrence of colorunevenness.

While the present invention has been described with reference toexemplary embodiments, it is to be understood that the invention is notlimited to the disclosed exemplary embodiments. The scope of thefollowing claims is to be accorded the broadest interpretation so as toencompass all such modifications and equivalent structures andfunctions.

This application claims the benefit of Japanese Patent Application No.2013-003477, filed Jan. 11, 2013, which is hereby incorporated byreference herein in its entirety.

What is claimed is:
 1. A process for producing a chip in which pluralejection orifice arrays are arranged, the process comprising the stepsof: conducting reduction projection exposure plural times to a waferhaving a substrate and a photosensitive resin layer formed on thesubstrate while relatively moving positions of the wafer and a reticleto form ejection orifice array patterns in the photosensitive resinlayer, developing the ejection orifice array patterns to form ejectionorifice arrays in the photosensitive resin layer, and dividing the waferhaving the photosensitive resin layer in which the ejection orificearrays have been formed to form plural chips in which the pluralejection orifice arrays are arranged, wherein the reduction projectionexposure is conducted once to form in the photosensitive resin layer afirst ejection orifice array pattern corresponding to partial ejectionorifice arrays in an arranging direction of ejection orifice arrays inone chip, a second ejection orifice array pattern corresponding to allejection orifice arrays in another one chip and a third ejection orificearray pattern corresponding to partial ejection orifice arrays in anarranging direction of ejection orifice arrays in a further one chip. 2.The process according to claim 1, wherein an ejection orifice arraypattern corresponding to all ejection orifice arrays in one chip isformed by the first ejection orifice array pattern formed by oneexposure and a third ejection orifice array pattern formed by next oneexposure conducted after positions of the wafer and the reticle arerelatively moved.
 3. The process according to claim 1, wherein the firstejection orifice array pattern and the third ejection orifice arraypattern have an ejection orifice array pattern corresponding to half ofall ejection orifice arrays in one chip.
 4. The process according toclaim 1, wherein the second ejection orifice array pattern has anejection orifice array pattern corresponding to three or more ejectionorifice arrays, and the three or more ejection orifice arrays includeejection orifice arrays for respectively ejecting liquids of differentcolors, and the ejection orifice arrays are arranged in such a mannerthat the color arrangement of the liquids becomes line symmetry whenviewed from an ejection orifice array located at the center.
 5. Theprocess according to claim 4, wherein the three or more ejection orificearrays have an ejection orifice array (C) for ejecting a cyan ink, anejection orifice array (M) for ejecting a magenta ink and an ejectionorifice array (Y) for ejecting a yellow ink, and the chip is constitutedin such a manner that the ejection orifice arrays are arranged in theorder of CMYMC.
 6. The process according to claim 5, wherein theejection orifice array (C) for ejecting the cyan ink, the ejectionorifice array (M) for ejecting the magenta ink and the ejection orificearray (Y) for ejecting the yellow ink are each constituted by twoejection orifice arrays.
 7. A chip in which plural ejection orificearrays are arranged, wherein the length of a central ejection orificearray among ejection orifice arrays constituting the plural ejectionorifice arrays is longest, and the ejection orifice arrays are arrangedin descending order of the length of the ejection orifice array from thecentral ejection orifice array toward ejection orifice arrays on bothsides.
 8. A chip in which plural ejection orifice arrays are arranged,wherein the length of a central ejection orifice array among ejectionorifice arrays constituting the plural ejection orifice arrays isshortest, and the ejection orifice arrays are arranged in ascendingorder of the length of the ejection orifice array from the centralejection orifice array toward ejection orifice arrays on both sides. 9.The chip according to claim 7, wherein the plural ejection orificearrays include ejection orifice arrays for respectively ejecting liquidsof different colors, and the ejection orifice arrays are arranged insuch a manner that the color arrangement of the liquids becomes linesymmetry when viewed from the central ejection orifice array.
 10. Thechip according to claim 8, wherein the plural ejection orifice arraysinclude ejection orifice arrays for respectively ejecting liquids ofdifferent colors, and the ejection orifice arrays are arranged in such amanner that the color arrangement of the liquids becomes line symmetrywhen viewed from the central ejection orifice array.